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1 features description applications iso150 www.ti.com .......................................................................................................................................... sbos032d ? september 2000 ? revised august 2008 dual, isolated, bidirectional digital coupler replaces high-performance optocouplers data rate: 80 m baud, typ the iso150 is a 2-channel, galvanically-isolated data coupler capable of data rates of 80m baud, typical. low power consumption: 25 mw per channel, each channel can be individually programmed to max transmit data in either direction. two channels, each bidirectional, data is transmitted across the isolation barrier by programmable by user coupling complementary pulses through high voltage partial discharge tested: 2400 vrms 0.4 pf capacitors. receiver circuitry restores the creepage distance of 7,2 mm pulses to standard logic levels. differential signal transmission rejects isolation-mode voltage transients low cost per channel up to 1.6 kv/ m s available in so package the iso150 avoids problems commonly associated ul 1577 certified with optocouplers. optically isolated couplers require high current pulses and allowance must be made for led aging. the iso150 ' s bi-cmos circuitry operates digital isolation for a/d, d/a conversion at 25 mw per channel. isolated rs-485 interface the iso150 is available in an so-28 and is specified multiplexed data transmission for operation from ? 40 c to 85 c. isolated parallel to serial interface test equipment microprocessor system interface isolated line receiver ground loop elimination 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. production data information is current as of publication date. copyright ? 2000 ? 2008, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. iso150 channel 2 channel 1 side a side b g a d 2a r/t 2a d 2b v sb r/t 2b d 1b g b r/t 1b v sa d 1a r/t 1a 28 27 26 17 16 15 1 2 3 12 13 14
absolute maximum ratings regulatory information iso150 sbos032d ? september 2000 ? revised august 2008 .......................................................................................................................................... www.ti.com this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ordering information (1) specified transport package package package ordering product temperature media, lead designator marking number range quantity iso150au rails, 28 iso150au so-28 dvb ? 40 c to 85 c iso150au iso150au/1k tape and reel, 1000 (1) for the most current package and ordering information, see the package option addendum at the end of this document, or see the ti website at www.ti.com . over operating free-air temperature range (unless otherwise noted) (1) (2) unit storage temperature ? 40 c to 125 c v s supply voltage ? 0.5 v to 6 v v i transmitter input voltage ? 0.5 v to v s + 0.5 v v o receiver output voltage ? 0.5 v to v s + 0.5 v r/ t x inputs ? 0.5 v to v s + 0.5 v v iso isolation voltage dv/dt 500 kv/ m s d x short to ground continuous t j junction temperature 125 c lead temperature (soldering, 10s) 260 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute maximum rated conditions for extended periods may affect device reliability. (2) this isolator is suitable for basic insulation applications within the safety limiting data. maintenance of the safety data must be ensured by means of protective circuitry. ul recognized under 1577 component recognition program (1) file number: e181974 (1) production tested at 2400 vrms for 1 second in accordance with ul 1577. 2 submit documentation feedback copyright ? 2000 ? 2008, texas instruments incorporated product folder link(s): iso150
electrical characteristics iso150 www.ti.com .......................................................................................................................................... sbos032d ? september 2000 ? revised august 2008 at t a = 25 c and v s = 5 v (unless otherwise noted) iso150au parameter test conditions unit min typ max isolation parameters rated voltage, continuous 60 hz 1500 vrms partial discharge, 100% test (1) 1s, 5pc 2400 vrms creepage distance (external) so-u package 7.2 mm internal isolation distance 0.10 mm isolation voltage transient immunity (2) 1.6 kv/ m s barrier impedance > 10 14 || 7 ? || pf leakage current 240 vrms, 50 hz 0.6 m arms dc parameters high, v oh i oh = 6 ma v s ? 1 v s logic output voltage v low, v ol i ol = 6 ma 0 0.4 logic output short-circuit current source or sink 30 ma high (3) 2 v s logic input voltage v low (3) 0 0.8 logic input capacitance 5 pf logic input current < 1 na power-supply voltage range (3) 3 5 5.5 v dc 0.001 100 m a transmit mode 50m baud 14 ma power-supply current (4) dc 7.2 10 receive mode ma 50m baud 16 ac parameters maximum (5) c l = 50 pf 50 80 data rate m baud minimum dc propagation time (6) c l = 50 pf 27 40 ns propagation delay skew (7) c l = 50 pf 0.5 2 ns pulse width distortion (8) c l = 50 pf 1.5 6 ns output rise-and-fall time, 10% to 90% c l = 50 pf 9 14 ns receive to transmit 13 ns mode switch time transmit to receive (9) 75 ns temperature range operating range ? 40 85 c storage ? 40 125 c thermal resistance, q ja 75 c/w (1) all devices receive a 1s test. failure criterion is 5 pulses of 5 pc. (2) the voltage rate-of-change across the isolation barrier that can be sustained without data errors. (3) logic inputs are hct-type and thresholds are a function of power-supply voltage with approximately 0.4 v hysteresis ? see text. (4) supply current measured with both transceivers set for the indicated mode. supply current varies with data rate ? see typical characteristics. (5) calculated from the maximum pulse width distortion (pwd), where data rate = 0.3/pwd. (6) propagation time measured from v in = 1.5 v to v o = 2.5 v. (7) the difference in propagation time of channel a and channel b in any combination of transmission directions. (8) the difference between propagation time of a rising edge and a falling edge. (9) when the device is powered up or direction is changed, the transceiver output is indeterminate (either high or low) and cannot be known until an input signal is applied. the output begins to track the input as soon as the input receives a change in logic state, either low to high or high to low. copyright ? 2000 ? 2008, texas instruments incorporated submit documentation feedback 3 product folder link(s): iso150
pin configuration terminal functions iso150 sbos032d ? september 2000 ? revised august 2008 .......................................................................................................................................... www.ti.com terminal description name no. d 1a 1 data in or data out for transceiver 1a, r/ t 1a held low makes d 1a and input pin. r/ t 1a 2 receive/transmit switch controlling transceiver 1a. v sa 3 +5v supply pin for side a, which powers transceivers 1a and 2a. g b 12 ground pin for transceivers 1b and 2b. r/ t 1b 13 receive/transmit switch controlling transceiver 1b. d 1b 14 data in or data out for transceiver 1b. r/ t 1b held low makes d 1b an input pin. d 2b 15 data in or data out for transceiver 2b. r/ t 2b held low makes d 2b an input pin. r/ t 2b 16 receive/transmit switch controlling d 2b . v sb 17 +5v supply pin for side b, which powers transceivers 1b and 2b. g a 26 ground pin for transceivers 1a and 2a. r/ t 2a 27 receive/transmit switch controlling transceiver 2a. d 2a 28 data in or data out for transceiver 2a, r/ t 21a held low makes d 2a an input pin. 4 submit documentation feedback copyright ? 2000 ? 2008, texas instruments incorporated product folder link(s): iso150 2827 26 17 1615 12 3 12 1314 d 1a r/t 1a v sa g b r/t 1b d 1b v sb r/t 2b d 2b d 2a r/t 2a g a t op v iew so
typical characteristics iso150 www.ti.com .......................................................................................................................................... sbos032d ? september 2000 ? revised august 2008 at t a = 25 c and v s = 5 v, unless otherwise noted. supply current per channel vs supply voltage power consumption per channel vs frequency figure 1. figure 2. typical rise and fall times vs capacitive load vs supply current per channel vs temperature supply voltage figure 3. figure 4. normalized rise-and-fall time vs temperature propagation delay vs supply voltage figure 5. figure 6. copyright ? 2000 ? 2008, texas instruments incorporated submit documentation feedback 5 product folder link(s): iso150 100 8060 40 20 0 capacitive load (pf) t r , t f (ns) v s = 3.0v v s = 5.0v t r t f t f t r 0 100 200 300 400 500 1.61.5 1.41.3 1.21.1 1.0 .9 relative t r , t f c l = 50pf normalized to average of many devices at 25 c +1 s 1 s t emperature ( c) 60 40 20 0 20 40 60 80 100 120 140 4540 3530 25 20 supply v oltage, v s (v) propagation delay (ns) low to high high to low pulse width distortion 2.5 3.0 3.5 4.0 4.5 5.0 5.5 frequency (hz) 100k 1m 10m 100m power (mw) supply current (ma) 100 8040 20 0 2016 12 8 4 receive transmit no loadone channel note: baud rate = 2 frequency 0 60 54 3 2 1 12345 6 supply v oltage, v s (v) supply current (ma) c l = 15pf receive mode t ransmit mode 0 f = 1mhz = 2mbaud 60 6 54 3 2 1 40 supply current (ma) v s = 5.0v v s = 3.0v t emperature ( c) 20 0 20 40 60 80 100 120 140
iso150 sbos032d ? september 2000 ? revised august 2008 .......................................................................................................................................... www.ti.com typical characteristics (continued) at t a = 25 c and v s = 5 v, unless otherwise noted. propagation delay vs temperature pulse width distortion vs temperature figure 7. figure 8. logic input threshold voltage vs supply output voltage voltage vs logic input voltage figure 9. figure 10. isolation leakage current vs frequency isolation voltage vs frequency figure 11. figure 12. 6 submit documentation feedback copyright ? 2000 ? 2008, texas instruments incorporated product folder link(s): iso150 2.1k 1k 100 10 1 frequency (hz) peak isolation v oltage (v) max dc rating degradedperformance 1 k 10 k 100 k 1 m 10 m 100 m 10m 1m 100m 10m 1m 100n frequency (hz) leakage current (arms) v iso = 240v rms v iso = 1500v rms 100m 1 10 100 1 k 10 k 100 k 1 m 5040 30 20 10 0 t emperature ( c) propagation delay , t pd (ns) v s = 3.0v v s = 5.0v c l = 50pf 60 60 40 20 0 20 40 60 80 100 120 140 54 3 2 1 0 pulse width distortion, pwd (ns) v s = 5.0 v c l = 50 pf t emperature ( c) 60 40 20 0 20 40 60 80 100 120 140 54 3 2 1 v in (v) v out (v) 0 0.5 1.0 1.5 2.0 supply v oltage, v ss (v) v in (v) v t low , 40 c v t high , 125 c 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.81.6 1.4 1.2 1.0 0.8 0.6 0.4 2.00.2 0
isolation barrier iso150 www.ti.com .......................................................................................................................................... sbos032d ? september 2000 ? revised august 2008 typical characteristics (continued) at t a = 25 c and v s = 5 v, unless otherwise noted. typical insulation resistance vs temperature figure 13. produced by localized ionization within the barrier; this is the most sensitive and reliable indicator of barrier integrity and longevity, and does not damage data is transmitted by coupling complementary logic the barrier. a device fails the test if five or more pulses to the receiver through two 0.4 pf capacitors. current pulses of 5pc or greater are detected. these capacitors are built into the iso150 package conventional isolation barrier testing applies test with faraday shielding to guard against false voltage far in excess of the rated voltage to triggering by external electrostatic fields. catastrophically break down a marginal device. a the integrity of the isolation barrier of the iso150 is device that passes the test may be weakened, and verified by partial discharge testing: 2400 vrms, 60 lead to premature failure. hz, is applied across the barrier for one second while measuring any tiny discharge currents that might flow through the barrier. these current pulses are copyright ? 2000 ? 2008, texas instruments incorporated submit documentation feedback 7 product folder link(s): iso150 w isolation resistance ( ) 10 16 10 15 10 14 10 13 10 12 10 11 10 10 0 20 40 60 80 100 120 140 160 180 t emperature ( c)
application information iso150 sbos032d ? september 2000 ? revised august 2008 .......................................................................................................................................... www.ti.com shown. the transmission direction can be controlled figure 14 shows the iso150 connected for basic by logic signals applied to the r/ t pins. channel 1 operation; channel 1 is configured to transmit data and 2 can be independently controlled for the desired from side b to a, whereas channel 2 is set for transmission direction. see figure 15 and figure 16 transmission from side a to b. the r/ t pins for each for application examples using the iso150. of the four transceivers are shown connected to the required logic level for the transmission direction figure 14. basic operation diagram figure 15. isolated rs-485 interface 8 submit documentation feedback copyright ? 2000 ? 2008, texas instruments incorporated product folder link(s): iso150 data in +5v (1) +5v (1) (1) (1) (2) (1) (1) (2) channel 2 data out channel 1 data out channel 2 data in channel 1 (transmit) (transmit) (receive) (receive) channel 2 channel 1 side a side b g a d 2a r/t 2a d 2b v sb r/t 2b d 1b g b r/t 1b v sa d 1a r/t 1a notes: (1) power supplies and grounds on side a and side b are isolated. (2) recommended bypass: 0.1 f in parallel with 1nf. data (i/o) de/re +5v o1o (+5v) re d r ab bus +5v +5v de sn65hvd05 channel 2 channel 1 side a side b g a d 2a r/t 2a d 2b v sb r/t 2b d 1b g b r/t 1b v sa d 1a r/t 1a
logic levels propagation delay and skew power supply mode changes standby mode power-up state circuit layout signal loss iso150 www.ti.com .......................................................................................................................................... sbos032d ? september 2000 ? revised august 2008 still, some applications with large, noisy isolation- mode voltage can produce data errors by causing the receiver output to change states. after a data error, a single pin serves as a data input or output, subsequent changes in input data will produce correct depending on the mode selected. logic inputs are output data. cmos with thresholds set for ttl compatibility. the logic threshold is approximately 1.3 v with 5 v supplies with approximately 400 mv of hysteresis. input logic thresholds vary with the power-supply logic transitions are delayed approximately 27ns voltage. drive the logic inputs with signals that swing through the iso150. some applications are sensitive the full logic voltage swing, note that the iso150 will to data skew ? the difference in propagation delay use somewhat greater quiescent current if logic between channel 1 and channel 2. skew is less than inputs do not swing within 0.5 v of the power-supply 2ns between channel 1 and channel 2. applications rails. using more than one iso150 must allow for in receive mode, the data output can drive 15 somewhat greater skew from device to device. as all standard ls-ttl loads. it will also drive cmos loads. devices are tested for delay times of 20ns min to the output drive circuits are cmos. 40ns max, 20ns is the largest device-to-device data skew. separate, isolated power supplies must be connected to side a and side b to provide galvanic isolation. the transmission direction of a channel can be nominal rated supply voltage is 5 v. operation changed on the fly by reversing the logic levels at the extends from 3 v to 5.5 v. power supplies should be channel's r/ t pin. note that when channel direction is bypassed close to the device pins on both sides of changed, the output state of the channel is the isolation barrier. indeterminate (either high or low) and cannot be known until an input signal is applied. the output the v s pin for each side powers the transceivers for begins to track the input as soon as the input both channel 1 and 2. the specified supply current is receives a change in logic state, either low to high or the total of both transceivers on one side, both high to low. operating in the indicated mode. supply current for one transceiver in transmit mode and one in receive mode can be estimated by averaging the specifications for transmit and receive operation. quiescent current of each transceiver circuit is very supply current varies with the data transmission rate low in transmit mode when input data is not changing ? see the typical characteristics. (1na typical). to conserve power when data transmission is not required, program both side a and b transceivers for transmit mode. input data applied to either transceiver is ignored by the other side. when the device is powered up or direction is high-speed data applied to either transceiver will changed, the transceiver output is indeterminate increase quiescent current. (either high or low) and cannot be known until an input signal is applied. the output begins to track the input as soon as the input receives a change in logic state, either low to high or high to low. the high speed of the iso150 and its isolation barrier require careful circuit layout. use good high speed logic layout techniques for the input and output data lines. power supplies should be bypassed close to the iso150's differential-mode signal transmission the device pins on both sides of the isolation barrier. and careful receiver design make it highly immune to use low inductance connections. ground planes are voltage across the isolation barrier (isolation-mode recommended. voltage). rapidly changing isolation-mode voltage can cause data errors. as the rate of change of maintain spacing between side 1 and side 2 circuitry isolation voltage is increased, there is a very sudden equal or greater than the spacing between the increase in data errors. approximately 50% of all missing pins of the iso150 (approximately 7mm). iso150s will begin to produce data errors with isolation-mode transients of 1.6kv/ m s. this may occur as low as 500 v/ m s in some devices. in comparison, a 1000 vrms, 60 hz isolation-mode voltage has a rate of change of approximately 0.5v/ m s. copyright ? 2000 ? 2008, texas instruments incorporated submit documentation feedback 9 product folder link(s): iso150
iso150 sbos032d ? september 2000 ? revised august 2008 .......................................................................................................................................... www.ti.com figure 16. the iso150 and the ads7807 are used to reduce circuit noise in a mixed-signal application 10 submit documentation feedback copyright ? 2000 ? 2008, texas instruments incorporated product folder link(s): iso150 28 27 24 22 21 17 16 15 13 12 11 10 9 14 19 18 1 3 2 4 5 6 7 8 25 26 23 20 14 11 10 12 13 15 1 2 3 4 5 6 7 9 14 11 10 12 13 15 1 2 3 4 5 6 7 9 v in v cc1 50k w 50k w 33.2 w 200 w 100 w 1m w +2.2 m f +2.2 m f r1 in r2 in agnd 1 cap ref agnd 2 sb/btc ext/int pwrd refd cs tag v dig vana busy r/c byte d0 d1 d2 d3 d4 d5 d6 d7 dgnd sdata sclk 100 w 100 w byte 100 w 100 w 100nf 10 m f 100nf 6.8 m f 1 w 1 w v cc1 +5v v cc1 +5v v cc2 +5v v cc2 +5v v cc1 +5v d 2a r/t 2a g a v sb r/t 2b d 2b d 1a r/t 1a v sa g b r/t 1b d 1b iso150 iso150 busy ser srclk srclr rclk g qa qb qc qd qe qf qg qh qh u2 r/c u3 high byte enable low byte enable v cc2 ser srclk srclr rclk g qa qb qc qd qe qf qg qh qh 74ls595 74ls595 d 2a r/t 2a g a v sb r/t 2b d 2b d 1a r/t 1a v sa g b r/t 1b d 1b v cc1 = v cc2 = +5v isolated supplies ads7807 +5v
iso150 www.ti.com .......................................................................................................................................... sbos032d ? september 2000 ? revised august 2008 revision history changes from original (august 1994) to revision a ..................................................................................................... page changed features bullet - from: plastic dip and soic packages to: available in so package ....................................... 1 changed from: iso150 is available in a 24-pin dip package to: the iso150 is available in an so-28. ........................... 1 changed from burr-brown to: burr-brown products from texas instruments (new layout). .............................................. 1 deleted the dip package from the ordering information table ............................................................................................ 2 deleted dip-p package from creepage distance (external) in the electrical characteristics table..................................... 3 deleted dip-p package illustration from the pin configuration. ............................................................................................ 4 changed pin configuration from: soic package to: so package ..................................................................................... 4 changed circuit layout paragraph from: iso150 (approximately 16mm for the dip version). sockets are not recommended. to: iso150 (approximately 7mm). ................................................................................................................ 9 changes from revision a (february 2003) to revision b ............................................................................................. page changed format and layout. ................................................................................................................................................. 1 added note 9 to the electrical characteristics table ............................................................................................................ 3 changes from revision b (february 2005) to revision c ............................................................................................. page added feature: ul 1577 certified. ........................................................................................................................................ 1 added table: regulatory information. ................................................................................................................................... 2 changes from revision c (october 2007) to revision d ............................................................................................... page changed abs max table - junction temperature from: 175 c to 125 c ............................................................................ 2 copyright ? 2000 ? 2008, texas instruments incorporated submit documentation feedback 11 product folder link(s): iso150
package option addendum www.ti.com 9-aug-2016 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples iso150ap obsolete pdip nvg 12 tbd call ti call ti iso150au lifebuy sop dvb 12 20 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 iso150au iso150au-1 obsolete soic dva 8 tbd call ti call ti iso150au/1k lifebuy sop dvb 12 1000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr iso150au ISO150AUG4 lifebuy sop dvb 12 20 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 iso150au (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width.
package option addendum www.ti.com 9-aug-2016 addendum-page 2 important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant iso150au/1k sop dvb 12 1000 330.0 24.4 10.9 18.3 3.2 12.0 24.0 q1 package materials information www.ti.com 18-aug-2014 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) iso150au/1k sop dvb 12 1000 367.0 367.0 45.0 package materials information www.ti.com 18-aug-2014 pack materials-page 2
mechanical data mpdi068 ? august 2001 1 post office box 655303 ? dallas, texas 75265 nvg (r-pdip-t12/24) plastic dual-in-line 4202644/a 08/01 0.150 (3,81) 0.115 (2,92) ?c? 0.005 (0,13) min 1/2 lead 4 pl 112 13 24 1.195 (30,35) 1.160 (29,46) 0.630 (16,00) 0.655 (16,64) 0.240 (6,10) 0.280 (7,11) 0.070 (1,78) 0.045 (1,14) 0.030 (0,76) 0.045 (1,14) 0.014 (0,36) 0.022 (0,56) 4 pl 0.010 (0,25) mc 0.210 (5,33) 0.195 (4,95) 0.115 (2,92) 0.300 (7,62) max 0.430 (10,92) 0.000 (0,00) 0.060 (1,52) 0.014 (0,36) 0.008 (0,20) 0.325 (8,26) 0.300 (7,62) index area 0.015 (0,38) min 0.100 (2,54) seating plane base plane max d d c c h h d e e c f f notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. dimensions are measured with the package seated in jedec seating plane gauge gs-3. d. dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 (0,25). e. dimensions measured with the leads constrained to be perpendicular to datum c. f. dimensions are measured at the lead tips with the leads unconstrained. g. pointed or rounded lead tips are preferred to ease insertion. h. maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 (0,25). i. distance between leads including dambar protrusions to be 0.005 (0,13) minimum. j. a visual index feature must be located within the cross?hatched area. k. for automatic insertion, any raised irregularity on the top surface (step, mesa, etc.) shall be symmetrical about the lateral and longitudinal package centerlines. l. controlling dimension in inches. m. falls within jedec-ms-001-be with exception of lead count.
mechanical data mpds105 ? august 2001 1 post office box 655303 ? dallas, texas 75265 dva (r-pdso-g8/28) plastic small-outline 4202103/b 08/01 index area 114 15 28 seating plane 17,70 18,10 7,60 7,40 10,01 10,65 2,35 2,65 0,30 0,10 0,51 0,33 0,32 0,23 0,25 0,75 x 45 1,27 0,40 0 ?8 c f g 1,27 0,25 m b a c s 0,10 0,25 m b c b a d m m notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body length dimension does not include mold flash, protrusions, or gate burrs. mold flash, protrusions, and gate burrs shall not exceed 0,15 mm per side. d. body width dimension does not include inter-lead flash or portrusions. inter-lead flash and protrusions shall not exceed 0,25 mm per side. e. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the cross-hatched area. f. lead dimension is the length of terminal for soldering to a substrate. g. lead width, as measured 0,36 mm or greater above the seating plane, shall not exceed a maximum value of 0,61 mm. h. lead-to-lead coplanarity shall be less than 0,10 mm from seating plane. i. falls within jedec ms-013-ae with the exception of the number of leads.
www.ti.com package outline c 8 0 typ 0.32 0.23 10.65 10.01 8x 1.27 12x 0.51 0.33 2x 16.51 2.65 max 0.3 0.1 1.27 0.40 a note 3 18.1 17.7 b 7.6 7.4 4222497/a 10/2015 sop - 2.65 mm max height dvb0012a plastic small outline notes: 1. all linear dimensions are in millimeters. dimensions in parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. this dimension does not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. reference jedec registration ms-013. 1 28 0.25 c a b 15 14 pin 1 id area seating plane 0.1 c see detail a detail a typical scale 0.900
www.ti.com example board layout (9.3) 0.07 max all around 0.07 min all around 12x (2) 12x (0.6) 8x (1.27) (r ) typ 0.05 (16.51) 4222497/a 10/2015 sop - 2.65 mm max height dvb0012a plastic small outline symm symm land pattern example scale:6x 1 14 15 28 notes: (continued) 5. publication ipc-7351 may have alternate designs. 6. solder mask tolerances between and around signal pads can vary based on board fabrication site. metal solder mask opening non solder mask defined solder mask details solder mask opening metal under solder mask solder mask defined
www.ti.com example stencil design (9.3) 8x (1.27) 12x (0.6) 12x (2) (r ) 0.05 (16.51) 4222497/a 10/2015 sop - 2.65 mm max height dvb0012a plastic small outline notes: (continued) 7. laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. ipc-7525 may have alternate design recommendations. 8. board assembly site may have different recommendations for stencil design. symm symm 1 14 15 28 solder paste example based on 0.125 mm thick stencil scale:6x
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